> 1st i got the data of 6 bit length > some other time when i get the data of length10 bit even in same way And HOW can cou see this difference of 4 bits on a 16 bit vector? How can you KNOW the witdh of the actual vector? > I think u got my point Yes, i do, but not vice versa. Thats exactly, what my previously posted code does. > Similarly some other time when i get the data of length10 bit even in > same way that should get serialized. > For example 1st i got the data of 6 bit length at > that time that data should be latched then it should get serialized. This means our logic should be 1 time programmed instead of runtime programmable. Similarly some other time when i get the data of length10 bit even in same way that should get serialized. Ya input is fixed length of 16 bit but this parallel to serial converter logic should be programmable when ever the data will arrive then dat should get serialized.įor example 1st i got the data of 6 bit length at that time that data should be latched then it should get serialized. ALL entity P2S is port ( Serial_out: out std_logic clk: in std_logic Parallel_data: in std_logic_vector( 15 downto 0) DataReady: in std_logic) end P2S architecture Behavioral of P2S is signal OldReady: std_logic:= '0' signal Shreg: std_logic_vector( 15 downto 0) begin process (clk) begin if (clk 'event and clk = '1') then Shreg.
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